1. Field of the Invention
The invention relates generally to test methods, and more particularly to systems and methods for providing improved fault coverage of scan tests, such as logic built-in-self-tests, in integrated circuits by controlling the data passing through certain components.
2. Related art
As digital devices (e.g., integrated circuits) have become more complex and more densely packed with logic gates and other electronic components, there are more and more opportunities for manufacturing defects to occur, thereby impairing or impeding the proper operation of the devices. Consequently, the testing of these devices is becoming increasingly important. With respect to the testing of devices, and more particularly manufactured integrated circuits (ICs), one mechanism that is very useful is a built-in self test (BIST). This may also be referred to as a logic built-in self test (LBIST).
BIST and LBIST methodologies are generally considered part of a group of methodologies referred to as design-for-test (DFT) methodologies. DFT methodologies involve incorporating features into the actual designs of the circuits to facilitate testing of the circuits. BIST methodologies involve incorporating circuit components into the design of the circuit to be tested, where the additional circuit components are used for purposes of testing the functional portion of the circuitry.
In a typical LBIST system, LBIST circuitry within a device under test includes multiple scan chains interposed between levels of the functional logic of the device. Typically, pseudorandom patterns of bits are generated and loaded into the scan chains. This may be referred to as scanning the data into the scan chains (during a scan shift phase). After a pseudorandom bit pattern is scanned into a scan chain, the data is propagated through the functional logic to a subsequent scan chain (during a functional phase). The data is then scanned out of the subsequent scan chain. The data may be compressed to reduce storage and bandwidth requirements. This test loop is typically repeated many times (e.g., 10,000 iterations,) with the results of each test loop being combined in some manner with the results of the previous test loops. For example, the results may be compared according to values in corresponding multiple input signature registers, or MISR's. After all of the scheduled test loops have been completed, the final result is compared to a final result generated by a device that is known to operate properly operated in an identical test (using identical input data processed identically.) Based upon this comparison, it is determined whether the device under test operated properly.
Because the use of pseudorandom patterns is not deterministic (i.e., it does not test each and every possible combination of inputs, states and outputs), it does not provide the simple result that the logic circuit either does or does not have any defects. Instead, it provides a level of confidence that the logic circuit does or does not have defects. The greater the number of inputs and states that are tested, the higher the confidence level that any defects have been identified by the testing. The number of random test patterns that are needed to achieve a particular level of confidence that the logic circuit contains no defects depends on the design of the logic circuit. This non-deterministic testing approach is typically easier and less expensive to implement than a deterministic approach.
Some components or portions of the circuitry, however, may require a very specific and improbable combination of bits to properly test the circuitry. For example, “large” AND gates have an output of 1 only when all of the inputs to the AND gate are 1's. It is therefore necessary for test purposes to ensure that all of the inputs to the AND gate will, at some point in the testing, be 1's. Because this is unlikely in a pseudorandom sequence of bits, it gives rise to concerns regarding the likelihood that all output states will be exercised during testing.
While it might at first appear to be possible to provide additional logic between the scan latches and the target logic to be tested in order to force the inputs to the target logic to desired values, this may violate timing constraints of the LBIST and/or target logic. For example, in the case of a many-input AND gate, the gate is actually constructed by cascading multiple two-input AND gates. Consequently, the time required for the inputs of the many-input AND gate to propagate through to its output is the sum of the times required for data to traverse each tier of the two-input AND gates that form the many-input AND gate. This time becomes even greater when the many-input AND gate is constructed using a NAND gate and an inverter in place of each two-input AND gate. Placing additional logic between the scan latches and the many-input AND gate may therefore not allow enough time for the data to propagate from the scan latches to the output of the many-input AND gate, causing errors in the testing.
There is therefore a need to provide systems and methods for forcing the values in selected LBIST scan latches to particular values in order to ensure adequate test coverage when a desired bit pattern is unlikely to occur in a pseudorandom bit sequence. There is further a need to provide systems and methods for this purpose, wherein the amount of time required for data to propagate from the scan latches to the output of the target logic is not increased.